Signal detector circuit

ABSTRACT

A circuit for detecting the presence or absence of a television receiving signal is disclosed, wherein a detection output for automatic frequency control is compared with first to fifth levels. A low-level output is produced when the detection output is lower than the fifth level; an intermediate-level output is produced when the detection output is between the fifth and fourth levels; a low-level output is produced when the detection output is between the third and second levels; an intermediate-level output is produced when the detection output is between the second and first levels; and a high-level output is produced when the detection output is higher than the first level, thus producing an output signal of three-digit level from a single output terminal.

The present invention relates to a signal detector circuit for a tuningdevice of automatic search type for television receivers, more inparticular to a circuit for detecting a receiving condition of abroadcast signal by use of a detection signal for automatic frequencycontrol (frequency discrimination signal).

In a tuning device of automatic search type, the locally oscillatedfrequency is changed with time so that the receiving frequency is swept,and when a particular signal is received at the time when apredetermined broadcast signal frequency is reached, the frequencysweeping is stopped thereby to continuously receive the particularfrequency. In this case, it is required to detect whether or not thereceiving frequency accurately coincides with the frequency of thebroadcast signal to attain the proper receiving state.

The features of the present invention will become apparent when readingthe following detailed description of the prior art and the presentinvention in conjunction with the accompanying drawings, in which:

FIG. 1 is a diagram showing a conventional signal detector circuit;

FIG. 2 is a time chart for explaining the operation thereof;

FIG. 3 is a diagram showing a signal detector circuit proposed prior tothe present invention;

FIGS. 4 and 5 are time charts for explaining the operation of thecircuit of FIG. 3;

FIG. 6 is a diagram showing a signal detector circuit according to anembodiment of the present invention;

FIG. 7 is a time chart for explaining the operation of the circuit shownin FIG. 6; and

FIG. 8 is a circuit diagram for explaining the operation of the circuitshown in FIG. 6.

First, a conventional signal detector circuit will be described withreference to FIG. 1. In FIG. 1, reference numeral 1 designates anintegrated circuit element (hereinafter referred to as IC) for thedetector circuit, numeral 2 a source voltage supply terminal thereof,and numeral 3 a grounding terminal. An AFC detection output A (S curveoutput) for automatic frequency control for the television receiver isapplied to an input terminal 4. This signal is subjected to an impedanceconversion through an emitter-follower made up of a transistor 5, andproduced through a diode 6 to a terminal 7 for supplying to the tunerAFC circuit on the one hand and applied to level converters (voltagecomparators) 8, 9 and 10 on the other hand.

A terminal 11 is applied with an input signal for turning on and off theAFC operation. When "AFC is turned off", it means that a fixed voltageof 6.5 V is applied to the AFC voltage supply terminal for the tuner,and when the "AFC is turned on", it means that PG,4 the AFC detectionoutput from the input terminal 4 is transmitted to the AFC voltagesupply terminal 7 for the tuner. Assume that the input to the terminal11 is at high level. A transistor 12 is conducting, a diode 13 is cutoff, and a transistor 14 is cut off. Therefore, the diode 6 isconducting, so that the AFC detection output supplied from the terminal4 makes up the output of the emitter-follower and is produced at theterminal 7 through the diode 6. This is the state of AFC turned on. Whenthe terminal 11 is at low level, on the other hand, the transistor 12 iscut off and the transistor 14 is conducting, so that the diode 6 is cutoff while the diode 13 is conducting. In other words, the fixed voltageof about 6.5 V divided by resistors 15 and 16 and the base-emittervoltage of the transistor 14 is produced at the terminal 7 for the tunerthrough the diode 13. This is the state of the "AFC turned off".

An AFC detection output A is applied to the + input terminal of each ofthe level comparators 8, 9 and 10, so that reference voltages B, C and Dare applied to the - input terminals thereof. It is here assumed that B,C and D are approximately 7.20 V, 6.50 V and 5.80 V respectively. As aresult, the comparators 8, 9 and 10 produce outputs E, F and Grespectively as shown in FIG. 2 at output terminals 17, 18 and 19.

A circuit 22 for discriminating the presence or absence of a televisionsignal will be described specifically later and will not be explainedhere in detail. The circuit 22 used an integrator circuit connected to aterminal 25 and the signal input to terminals 23 and 24, in such amanner that in the presence of a television signal, the comparator 20produces a signal of low level, whereas in the absence of a televisionsignal, the comparator 20 produces a signal of high level at theterminal 21.

As described above, the conventional circuits comprising integratedcircuits require pins in a greater number of 12, thus requiring a DIL(dual in line) package.

Accordingly, it is a principal object of the present invention toprovide a circuit using a reduced number of pins.

In the prior art circuits, four signal detection output terminals arerequired, whereas according to the present invention using a tristate,only one signal output terminal is required while at the same timemaking the interface with external circuits more stable and accurate.The center level concerns the case in which the output W or the signal(i) changes from low to high or high to low. At the time of change fromhigh to low to intermediate to low, (M=intermediate level), the AFCdetection output is lower than the fifth level L, while at the time oflevel change from low to high to intermediate to high, the AFC detectionoutput is higher than the first level H. This fact can be easilydiscriminated by the microcomputer or the like.

According to the present invention, the employment of integratedcircuits is made possible by reducing the number of pins on the onehand, and the signal detection is facilitated through the interface onthe other hand.

A previously proposed signal detector circuit is shown in FIG. 3, andwaveforms produced at various parts thereof are shown in FIGS. 4 and 5respectively.

The circuit of FIG. 3 uses nine pins, and the SIL (single in line)package thereof is possible when employing integrated circuits, thusreducing the cost considerably. The parts concerning the AFC on and offare identical to those in the conventional circuits and are denoted bythe same reference numerals without being explained.

In this circuit, the AFC detection output A is applied to fivecomparators 26 to 30 thus providing one input for comparison at fivelevels with the input supplied on the other side in the form of first tofifth reference voltages H, I, J, K and L. Assume that a value of H isdetermined to be about 7.9 V, a value of I about 7.2 V, a value of Jabout 6.5 V, a value of K about 5.8 V and a value of L about 5.1 Vthrough a resistor 31 and diodes 32 to 36. A comparator 26 produces anoutput waveform M as shown in FIG. 4, and a comparator 27 produces anoutput waveform N as shown in the same drawing. Also, a comparator 28produces an output O. The outputs N and O are applied to an AND gate 37thereby to produce an output R therefrom. A comparator 29, on the otherhand, produces an output P. The reversed output of the signal O and theoutput P are applied to an AND gate 39 thereby to produce an output Ttherefrom. The output T and the output Q of a comparator 30 are appliedto an OR gate 40 thereby to produce an output U.

Assume that the presence of a television signal is detected due to a lowlevel of the output V of the comparator 20. In the case where the outputS is at high level, a transistor 41 is conducting. If the output U is athigh level at this time, a transistor 42 conducts and therefore theoutput W to an output terminal 43 is reduced to low level, while if theoutput U is at low level, the output W is raised to high level. In thecase where the output S is at low level, on the other hand, thetransistor 41 is cut off, so that if the output U is at high level, theoutput W is reduced to low level, while if the output U is at low level,the output W is maintained at intermediate level. In other words,according to the waveforms of the outputs S and U, the waveform as shownby (W) in FIG. 4 is produced as a detection output. In the absence of adetection signal where the output V of the comparator 20 is at highlevel, by contrast, transistors 44 and 45 conduct so that thetransistors 41 and 42 are cut off. Thus the output W is maintained atintermediate level, that is, the power supply is divided by externalresistors 46 and 47.

A circuit for detecting the presence or absence of a television signalwill be described with reference to FIG. 3 and the timing diagram ofFIG. 5. Reference numeral 48 designates an input terminal for theflyback pulse a', and numeral 49 an input terminal for a horizontalsynchronizing signal b'. The flyback pulse a' is differentiated by adifferentiator circuit 50 which produces an output c'. The horizontalsynchronizing signal b' is differentiated by a differentiator circuit 51which produces an output d'. During the negative state of the outputpulse d', a transistor 52 is temporarily cut off and the othertransistors conduct. In the presence of a television signal, thehorizontal synchronizing signal b' is in phase with the flyback pulsea', and therefore a detection output e' is raised to high level as shownin FIG. 5. This signal is integrated by a filter, and compared in levelby the comparator 20, thus producing the detection output V. A capacitor53 and a resistor 54 make up the filter and resistors 55 and 56 are forgenerating a reference voltage l'.

As described above, according to the previously proposed circuit onlyone signal output terminal is required by use of the output of atristate unlike in the conventional circuits requiring four outputterminals. The center level representing the receiving frequency capableof receiving the broadcast signal acurrately is such that the output Wchanges from low to high or high to low. At the time of change from highto low to intermediate to low (M: intermediate level), the AFC detectionoutput is lower than the fifth level L, while at the time of change fromlow to high to intermediate to high, the AFC detection output is higherthan the first level H. These facts are very easily detected by themicrocomputer or the like.

Although the specific example of the circuit shown in FIG. 3 fulfillsthe principal object mentioned above, the employment of integratedcircuits poses an inconvenience. Specifically, the source voltage of thepower terminal 2 rarely coincides with the high level voltage of theinput signal of the integrated circuit receiving the detection outputsignal, but in almost all cases, the interface between them isunsuccessful. In the circuit of FIG. 3, in order for the source voltage2 of IC to coincide with the high level of the other end receiving theoutput signal thereof, the resistors 46 and 58 connected to a separatepower supply of the power terminal 57 are used to control the highlevel. Nevertheless, in view of the variations of the resistance valueand the voltages of the power terminals 2 and 57, the performancestanders are often unsatisfied.

A circuit according to an embodiment of the present invention in whichthe level of the compared output, especially the high level can besecured by taking the interface into consideration will be describedbelow.

A specific circuit example of such an embodiment will be explained withreference to FIG. 6.

The switching circuit for AFC operation and the discriminator circuit 22for detecting the presence or absence of a television signal areidentical to those mentioned above and will not be described again.

An AFC detection output A from an input terminal 4 is applied through anemitter-follower 5 to the + input of a level comparator 26, the + inputof a level comparator 27, the + input of a level comparator 28, the +input of a level comparator 29 and the + input of a level comparator 30respectively. Reference voltages H, I, J, K and L generated by diodes32, 33, 34, 35 and a Zener diode 36 are applied to the - input of thelevel comparator 26, the - input of the level comparator 27, the - inputof the level comaprator 28, the - input of the level comparator 29 andthe - input of the level comparator 30 respectively. The referencevoltages H to L from the comparators 26 to 30 are compared with the AFCdetection output A, thereby producing output signals as shown in (a),(b), (c), (d) and (f) of FIG. 7 respectively.

The signals (a) and (b) are applied to a NOR gate 60, and the signals(d) and (e) are applied to another NOR gate 13. The output (f) of theNOR gate 60 and the output (h) of the NOR gate 13 are applied to an ORgate 61 for producing the signal (i). The signal (c) and the reversal(g) of signal (d) are applied to a NOR gate 64 for producing the output(j). This signal (j) and the signal (e) are applied to an OR gate 65 forproducing the signal (k). The outputs (h) and (i) thus obtained are usedto synthesize a three-digit output. A method of synthesizing athree-digit output will be described in simple manner with reference toFIG. 8.

Switching elements of FIG. 8 are designated by numerals corresponding tothose of the transistors in FIG. 6. First, in the case of producing ahigh level output, the switching elements take the state as shown in theleft section of FIG. 8 in which switching elements 72, 70 and 67 are allopen and the level at a terminal 43 is dependent solely on a voltage ata source voltage terminal 75. For attaining an intermediate level, theswitching elements take the state as shown in the middle section of FIG.8, in which the switching elements 72 and 70 are closed while theswitching element 67 is open, so that the level is synthesized byresistors R₁, R₂ and R₃. In the case of low level, on the other hand,the switching elements assume the state as shown in the right section ofFIG. 8, in which the switching elements 72 and 70 are open and theswitching element 67 is closed to provide a ground level. Only in thecase of the intermediate level output, both the voltages from the powersource terminals 2 and 75 are influential, but if the impedance of theresistors R₁ and R₂ is designed to have a reduced value as compared withthe resistance value R₃ of a resistor 45, the circuit is substantiallyfree of the effect of the voltage at the source voltage terminal 75. Itwill be seen that in the case of the three-digit output, the opening andclosing operations of the switching elements 72 and 70 are interlockedwith each other.

Returning to FIG. 6, assume that there is a television signal applied.The output V of the comparator 20 is low in level and transistors 66, 69and 71 are cut off. It will be seen from the timing diagram of FIG. 7that both the outputs (i) and (k) are never at high level at the sametime. In the case where the output (i) is at high level and the output(k) is at low level, on the other hand, a transistor 68 conducts,namely, a transistor 72 conducts, and also a transistor 70 conducts. Thetransistor 67 is cut off. This is the state of the middle section ofFIG. 8, thus attaining the intermediate level as mentioned above.

In the case where the output (i) is at low level and the output (k) isat high level, by contrast, the transistors 68 and 70 are cut off. Atransistor 72 is also cut off, while the transistor 67 conducts, thusattaining the state of the right section of FIG. 8. As a result, a lowlevel output is produced.

When both the outputs (i) and (k) are at low level, the transistors 68,70 and 67 are cut off. The transistor 72 is also cut off, thus attainingthe state shown in the left section of FIG. 8. In this case, a highlevel output is produced.

In this way, a signal as shown in (l) of FIG. 7 is produced. In theabsence of a television signal, the output V of the comparator 20 forsignal discrimination is at high level. Therefore, the transistors 66,69 and 71 conduct. The transistor 72 also conducts, while the transistor67 is cut off, thus attaining the state as shown in the middle sectionof FIG. 8, namely, the intermediate level.

What is claimed is:
 1. A signal detector circuit comprising: means forcomparing a detection output for automatic frequency control with firstto fifth levels respectively, wherein with a result that a low-leveloutput is produced when said detection output is lower than said fifthlevel, an intermediate-level output is produced when said detectionoutput is between said fourth and fifth levels, a low-level output isproduced when said detection output is between said third and fourthlevels, a high-level output is produced when said detection output isbetween said second and third levels, an intermediate-level output isproduced when said detection output is between said first and secondlevels, and a high-level output is produced when said detection outputis higher than said first level, an intermediate-level output beingproduced in the absence of a signal;a series circuit of a firstswitching element and a first resistor inserted between an outputterminal and a power terminal for said comparison means; a thirdswitching element connected in parallel to a series circuit of a secondswitching element and a second resistor, said parallel circuit beinginserted between said output terminal and the ground; and a thirdresistor inserted between said output terminal and a power supplyterminal of an external circuit for receiving the output of saidcomparator circuit, wherein said first, second and third switchingelements being all opened when said comparing means produces said highlevel output, said first and second switching elements are selectivelyclosed when said comparator circuit produces said intermediate-leveloutput, said third switching element being selectively closed when saidcomparing means produces said low-level output.
 2. A signal detectorcircuit according to claim 1, wherein a horizontal synchronizing signalextracted from a received television signal and a flyback signal aresynthesized, and the synthesized output is used to detect the presenceof the receiving signal, an intermediate-level output being produced inthe absence of said receiving signal.